Publications
2022 - Present
Microelectronics Reliability · 2023
Abstract: Compared with bulk technologies, Fully-depleted silicon-on-insulator (FD SOI) technology nodes show better resistance to single-event upsets. However, additional hardening techniques should be investigated to mitigate upsets at this technology node. Single-event (SE) performance of multiple hardened flip-flop (FF) designs based on Schmitt-trigger circuits along with a conventional DFF design in a 22-nm FD SOI process is presented. FF designs were tested using alpha particles and heavy-ions. Results show significant reductions in SEU cross-sections compared with the conventional design. Alpha particle exposures showed zero upsets for all FF designs tested. Schmitt-trigger-based FF designs showed from 2× to 200× improvement in heavy-ion SEU cross-sections compared with the conventional DFF design.
Microelectronics Reliability · 2023
Abstract: This study evaluates the sensitivity of FPGA-based CNN systems and the efficacy of selective hardening approaches with laser injection and proton irradiation. The LeNet-5 CNN architecture was taken as a case study. First, the entire CNN with block random access memory (BRAM) attached is evaluated by laser test scanning, and errors generated from each layer are detected to determine the most critical layer. Second, the same network is evaluated without BRAM, considering only the configuration RAM (CRAM) and errors generated from each layer are detected. Third, the impact of laser scan errors from BRAM and CRAM are compared, while tracing the layers in which these errors are generated. Then, proton testing is performed on the entire CNN, and errors from each layer are detected and compared to validate the laser scanning test. Experimental results from laser and proton demonstrate that CRAM errors have a larger impact on CNN layers than BRAM errors. Regarding layer criticality, the second convolutional layer (C2) appears to be the most critical one because it generates most CRAM errors. This was validated by serial and parallel designs, where both confirm similar trends. Accordingly, the partial triple modular redundancy (TMR) approach is only applied to the critical portions, leading to around 40 % reliability improvement with less than 20 % overhead.
IEEE Transactions on Nuclear Science · 2023
Abstract: Because of the isolation of transistors, fully depleted silicon-on-insulator (FDSOI) technology nodes have shown better single-event upset (SEU) resilience compared with bulk technology nodes. Additional radiation-hardening-by-design (RHBD) techniques can further improve the SEU performance. In this article, the SEU performance of multiple RHBD flip-flop (FF) designs using the guard-gate (GG) circuit at a 22-nm FDSOI technology is presented, including a conventional FF, a GG FF, a dual-feedback-recovery (DFR) FF, and a GG-dual-interconnected storage cell (DICE) FF. Irradiation results showed significant reductions in SEU cross sections for hardened designs compared to the conventional design. Specifically, the conventional GG design demonstrates more than
IEEE Transactions on Nuclear Science · 2023
Abstract: Embedded Silicon Germanium (eSiGe) is used in the channel region of PFET devices at the 22-nm FD SOI node. The use of eSiGe results in channel regions becoming strained, which results in better hole mobility and increased performance. However, if the active diffusion regions are too short on each side of a PFET gate, then the effect of channel strain is reduced, and performance is reduced. The Continuous Active Diffusion (CnRx) layout construct suggested by the foundry is a way to help keep channel strain present within a single-cell design. In this article, the CnRx construct is implemented in a 22-nm FD SOI test chip and soft error rates (SER) of stacked-transistor flip-flops (FFs) are shown to increase with heavy ion irradiation. The effect of channel strain on PFETs results in higher collected charges from ion strikes, and charges are more easily passed between adjacent transistors through strained channels. However, with careful schematic and layout design, these effects can be mitigated to produce both high-performance and radiation-tolerant cells using the CnRx construct.
IEEE Transactions on Nuclear Science · 2023
Abstract: Fully-depleted silicon-on-insulator (FDSOI) technology nodes offer better single-event (SE) performance compared with comparable bulk technologies. However, upsets are still possible at nanoscale feature sizes and additional hardening techniques need to be explored. This article presents the single-event upset (SEU) performance of multiple flip-flop (FF) designs using the stacked-transistor hardening technique at a 22-nm FDSOI technology node. Irradiation results show significant reductions in SEU cross sections for stacked-transistor-based hardened designs compared to a conventional design. Alpha particle exposures showed zero upsets for all D-flip-flop (DFF) designs tested. When exposed to heavy-ions, the stacked-transistor DFF design showed a
MDPI · 2022
Abstract: Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.
Applied Sciences · Apr 22, 2022
Abstract: Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should be explored. Three flip-flop designs were implemented using Dual Interlocked Cell (DICE) latches in a 22 m FD SOI technology node. Additional hardening was implemented in the layout of each design by using transistor spacing and interleaving. Comparisons were made between a standard DICE design and two other designs making use of the new Continuous Active (CnRx) Diffusion construct and guard-gate transistor stacking through alpha particle and heavy ion irradiation. Designs making use of the CnRx construct for performance improvements were more likely to experience upsets due to higher collected charges in the increased diffusion regions. Conversely, transistor stacking showed strong soft error rate resilience because of the natural isolation between transistors in the FD SOI technology. Overall, the efficacy of transistor interleaving in flip-flops using DICE latches was found to be extremely robust in the 22 nm FD SOI technology node.
2019-2021
Microelectronics Reliability · 2021
Abstract: Microprocessors are widely used in space applications. ARM processors fabricated with FDSOI technologies are promising for future space programs. However, radiation-hardening approaches can greatly affect the resource overhead and performance. These hardening techniques need to be evaluated at system level to better understand their effectiveness, especially for modern CMOS technologies. In this paper, two ARM® Cortex® M0 cores, a reference core and a hardened core were implemented on the same die in a 28-nm FDSOI technology. The reference core was designed with components from the standard cell library, while the other one was implemented with hardened DICE flip-flops. Both of the cores shared the same on-chip TMR-protected SRAM. Heavy ion experiments showed that the error cross section of the core with DICE flip-flops was about 2 times smaller at LET of 40 MeV·cm2·mg−1. This suggests that the contribution from logic circuits in the microprocessor cores also need to be considered for better error reduction.
Journal of Electronic Testing · 2021
Abstract: A triple modular redundancy SRAM was designed as the embedded high-speed memory for a radiation-tolerant ARM processor with ST Microelectronics 28-nm FDSOI technology. The single event upset (SEU) cross-section of the SRAM was tested by using heavy ions with the linear energy transfer of 15.0 meV.cm2.mg−1 in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using Cogenda TCAD simulation suite and the cross section was calculated by using analytic method. The results showed the cross-section is around 2E-10 cm2/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specific accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the Failure In Time (FIT) rate at sea level in New York City could be as low as 8E-11, which is robust enough for the whole circuit.
Journal of Electronic Testing · 2021
Abstract: In this paper, eight different SRAM cells are studied and evaluated with a 65nm CMOS technology. The cells were designed with radiation-hardening-by-design approaches including schematic and layout techniques. The eight types of cells were placed into eight pages of an SRAM test chip. The alpha and proton irradiation demonstrated that the Dual Interlocked Cell (DICE) has the best radiation-tolerant performance, but requires the largest area. The 6T and 11T cells designed with charge cancellation techniques can reduce soft errors up to 2-3 times with less area overhead. Several DICE variants were developed with reduced area overhead and showed SEU resilience performance equivalent to DICE. Simulation results are also presented in this paper to validate the findings.
MDPI · 2021
Abstract: Single event effect (SEE) and space electrostatic discharge (SESD) are two important types of effects causing spacecraft anomalies. However, it is difficult to differentiate them to identify the root cause of on-orbit anomalies. This paper pioneers the comparative study of the “soft errors” induced by the SEE and SESD with a well-known static random-access memory (SRAM). The similarity and difference of the physical mechanisms between the “soft errors” induced by SEE and SESD are studied with the technology computer-aided design (TCAD) simulations. Meanwhile, the characteristics of the “soft errors” and the relation with external stimulus between SEE and SESD are further investigated with the pulsed laser SEE facility and SESD test system. The results showed that the similar appearances of “soft errors” can be generated by both SEE and SESD, while multiple-bit upset (MBU) has been observed only in SESD testing. In addition, in comparison to the random distribution of SEE sensitivity areas, the SESD sensitivity areas are in closer proximity to the power supply regions. The different symptoms in upsets can be used to identify the root causes of the spacecraft anomalies.
IEEE Transactions on Nuclear Science · 2020
Abstract: Two-photon absorption laser experiments are conducted on a low-jitter tunable hybrid analog-digital LC-tank phase-locked loop (PLL) in a 28-nm bulk CMOS technology. The single-event effect (SEE) sensitivities for different blocks as well as the effect of varying circuit parameters are analyzed. The analog loop filter and the inductor-varactor area in the voltage-controlled oscillator (VCO) LC tank are identified as the most sensitive areas of the PLL, which generally agrees with previous studies. The VCO tail common-mode node, which was previously shown to be highly sensitive to SEE, exhibits very good robustness, thanks to the proposed second-order harmonic LC tail filter added in this design. The laser experiments show that a lower PLL bandwidth tends to reduce the SEE sensitivities of the PLL, while the results on the effect of the VCO frequency are mixed and need further study.
Applied Sciences · 2020
Abstract: Research on single event effects (SEEs) is significant to the design and manufacture of modern electronic devices. By applying two photon absorption (TPA) ultra-fast pulsed lasers, extra electron-hole pairs (EHPs) are generated in a desired location on a chip, simulating the process that could occur in the circuit by energetic particles. In this study, a SEE sensitivity mapping system is described which uses this method to generate real-time sensitivity maps for various electronic devices. The system hardware includes an attenuator to control the energy, a Pockels cell as a fast-optical switcher and a mirror–mirror module to project the laser beam into a certain location. The system software developed for this application controls the laser system, automatically generates sensitivity maps, communicates with the testing devices and logs the SEE results. The two main features of this laser mapping system are: high scanning velocity for large area scanning (about 1 × 1 mm) and high spatial resolution for small area scanning (about 1 × 1 μm). To verify this mapping system, sensitivity maps were generated for static random access memory (SRAM) built with 65 nm technology and for commercial operational amplifiers (op-amps). The achieved sensitivity maps were compared with circuitry analysis and laser testing results, confirming this mapping system to be effective.
IEEE Transactions on Device and Materials Reliability · 2020
Abstract: Research on single event effects (SEEs) is significant to the design and manufacture of modern electronic devices. By applying two photon absorption (TPA) ultra-fast pulsed lasers, extra electron-hole pairs (EHPs) are generated in a desired location on a chip, simulating the process that could occur in the circuit by energetic particles. In this study, a SEE sensitivity mapping system is described which uses this method to generate real-time sensitivity maps for various electronic devices. The system hardware includes an attenuator to control the energy, a Pockels cell as a fast-optical switcher and a mirror–mirror module to project the laser beam into a certain location. The system software developed for this application controls the laser system, automatically generates sensitivity maps, communicates with the testing devices and logs the SEE results. The two main features of this laser mapping system are: high scanning velocity for large area scanning (about 1 × 1 mm) and high spatial resolution for small area scanning (about 1 × 1 μm). To verify this mapping system, sensitivity maps were generated for static random access memory (SRAM) built with 65 nm technology and for commercial operational amplifiers (op-amps). The achieved sensitivity maps were compared with circuitry analysis and laser testing results, confirming this mapping system to be effective.