Ebrahim Fard

Ebrahim designs power-efficient hardware for deep learning on FPGAs, spanning the arithmetic building blocks that neural networks are built from and complete models compact enough to run on the constrained devices they protect.

Publications

FlexPWL: a flexible, scalable and multiplier-free approach for activation functions on FPGA

E. Fard, J. Arias-Garcia, H. Zhang, S.-B. Ko. IEEE Transactions on Computers, 75(8):3031, 2026.

• Sigmoid and Tanh are a bottleneck when recurrent networks are deployed on FPGAs, where multipliers are scarce and the functions are expensive to evaluate directly
• A piecewise linear approximation with new formulations for the y-intercept lowers both mean squared error and maximum absolute error at no additional hardware cost
• Dropping the segment address encoder and replacing the multiplier with a barrel shifter leaves a design that pipelines cleanly for low latency and high clock frequency
• A single unified architecture serves both functions and stays configurable in bit width, segment count and input range, so it can be retargeted across precision and hardware budgets
• Up to 18.52× better accuracy, 437.29× lower latency and 3.71× higher frequency than prior designs, using up to 11.63× fewer LUTs and 12.42× fewer flip-flops

LightIDS: a lightweight neural network-based intrusion detection system

E. Fard, M. Soltani, A. H. Jahangir, S.-B. Ko. The Journal of Supercomputing, 82:18, 2026.

• Intrusion detection is most needed on exactly the small networked devices that cannot host a GPU-scale model
• Design space exploration shrinks a state-of-the-art reference network to a far smaller one without giving up training speed or the ability to evaluate at scale
• On CIC-IDS2017 the compact model gives up only 1.48% precision, 0.21% recall and 0.76% F1-score; on CSE-CIC-IDS2018 it beats the same baseline by 5.87%, 1.25% and 3.34%
• The result is 275× smaller, 37× faster and 5.39× more power efficient than the GPU-based reference